The present invention relates to a MOS random access memory (RAM), and particularly to an improvement in the configuration of data bus lines of a large capacity MOSRAM.
FIG. 1 shows a configuration of data bus lines of a conventional MOS dynamic RAM. In recent years, the capacity of MOS dynamic RAMs is increasing. With that, the time required for testing a RAM is increasing and being more problematical. Various schemes have been proposed to reduce the test time. For instance, in the ISSCC Digest Technical Papers (1985); p. 240; M. Kumanoya et al., it is proposed to treat a 1-M bit DRAM of a .times.1 configuration as a memory of .times.4 configuration during test mode. With the .times.4 configuration for the test mode the memory cell array are divided into four blocks, and part (two bits) of the address code are used to select one of the four blocks while the rest of the address code is used to select one of the memory cells in each block. When for instance reading data by application of an address code, four bits of data are read out of the corresponding memory cells (addressed by the above-mentioned "rest of the address code") of the four blocks onto four pairs of I/O lines and only one of switches connected to the I/O lines are made conductive by the above-mentioned "part of the address code", so that only one of the four bits are output from the memory cell array.
FIG. 1 shows a MOS DRAM of a .times.1 configuration having a test mode function of a .times.4 configuration. In the figure, the MOS DRAM comprises a memory cell array 1, four preamplifiers 2 for detecting and amplifying data on four pairs of complementary data I/O lines 7 read out of the memory cell array 1, a mode controller 3 for switching between a normal mode and a test mode, a test controller 4 for providing signals for the test mode operation, a block selector 5 for secting one of the four outputs (data) read out during the normal mode and a buffer 6 in the form of an exclusive-OR gate receiving the four outputs (data) during the test mode and outputting test data.
During the normal mode operation, the mode controller 3 is kept in the normal mode under control of the test controller 4. In this state, data are read out of the memory cell array 1 onto the four pairs of complementary I/O lines 7, and are detected and amplified by the preamplifiers 2. The four data are then read out by the block selector 5 and one of the four data corresponding to the address then being supplied is output. If the memory cell array 1 consists of N memory cells or N bits, the time required for reading all the bits is EQU (cycle time tc).times.N=N.multidot.tc
During the test mode operation, the four data are similarly supplied via the I/O lines 7 to and amplified at the preamplifiers 2. The test controller 4 then provides a test control signal, upon which the mode controller 3 operates in the test mode. The four data are then supplied to the exclusive-OR buffer 6, and the test result is output. The time required for reading all the bits is EQU N.multidot.tc/4
Writing data is achieved by inputing data via the Din terminal, the block selector 5, the mode controller 3 and the pairs of the I/O lines 7. In the normal mode, the data is supplied to the memory cell array 1 through one of the pairs of the I/O lines 7. In the test mode, the same data are supplied to the memory cell array 1 through the four pairs of the I/O lines 7 to the four bits (four memory cells). Thus, the time required for writing in the test mode is 1/4 of the time required for writing in the normal mode.
The concept of using the .times.4 configuration in the test mode can be hypothetically extended to a .times.8 configuration, a .times.16 configuration, etc. to cope with further increase in the capacity of memories. But this leads to increase in the number of the I/O lines disposed in parallel with each other on the chip surface, e.g., 8 pairs, 16 pairs, etc., and increased complexity of the bus line configuration and increased chip surface area.